Ucie Spec Upd Jun 2026

| Layer | Function | |-------|----------| | | Electrical signaling, clocking, link training, PHY logic. | | Die-to-Die Adapter Layer | Link management, parameter negotiation, error detection/recovery (CRC, retry). | | Protocol Layer | Maps standard protocols (PCIe, CXL, Streaming) onto UCIe. |

| Type | Bump Pitch | Bandwidth Density (per mm edge) | Package Technology | |------|------------|--------------------------------|---------------------| | | 10–25 µm | >10 Tbps/mm | Hybrid bonding, face-to-face die stacking | | UCIe-2.5D | 25–55 µm | ~3 Tbps/mm | Silicon interposer (CoWoS, EMIB) | | UCIe-2D | 55–130 µm | ~1 Tbps/mm | Standard organic substrate |

UCIe defines three (pinouts) for interoperability: ucie spec

As Moore’s Law slows, chiplet-based disaggregated System-on-Chips (SoCs) offer the path to higher performance, yield, and reusability. UCIe provides the "glue" to mix compute, memory, I/O, and analog chiplets from multiple sources.

UCIe leverages established standards such as PCI Express (PCIe) and Compute Express Link (CXL). It also supports "Streaming Protocols" for proprietary or specialized data types. Key Iterations of the UCIe Spec | Layer | Function | |-------|----------| | |

The UCIe specifications have evolved rapidly to meet massive data demands: Introduction to UCIe™

Full protocol stack reuse (PCIe/CXL), ecosystem, and multi-vendor bump map. | | Type | Bump Pitch | Bandwidth

In March 2022, industry giants like formed the UCIe Consortium to create an open standard for "chiplets". Instead of one giant chip, designers could now connect smaller, specialized "tiles" (like LEGO bricks) from different manufacturers onto a single package. The Evolution of the Spec

Three primary protocol modes:

The UCIe specification is after registration at: https://www.uciexpress.org/specification