Pci Express Base Specification Revision 6.0 [top]

| Feature | PCIe 6.0 | CXL 3.0 (over PCIe 6.0) | Ethernet 800G | NVLink 4.0 | | :--- | :--- | :--- | :--- | :--- | | | 64 GT/s | 64 GT/s | 106.25 Gb/s | 100 Gb/s | | Protocol | Memory/IO | Coherent memory | Packet | GPU direct | | Latency | ~50 ns (FLIT) | ~80 ns | >200 ns | ~40 ns | | Topology | Tree | Fabric | Switch mesh | Fully connected | | Use Case | Universal | Memory pooling | Networking | GPU-only |

PCIe 6.0 controllers and devices support: pci express base specification revision 6.0

The link training and equalization process has been overhauled for PAM-4: | Feature | PCIe 6

| Feature | PCIe 5.0 | PCIe 6.0 | | :--- | :--- | :--- | | | LFSR for 128b/130b | LFSR for FLITs | | Deskew | Across lanes using SKP OS | Across lanes using FLIT markers | | Clock Tolerance | ±300 ppm | ±300 ppm (same) | | Lane Polarity Inversion | Supported | Supported | | Low Power States | L0s, L1, L2 | L0s, L1, L2 (modified entry/exit) | L2 | L0s

The PCI Express (PCIe) Base Specification Revision 6.0 is a standard for high-speed interconnects used in computers and other electronic devices. The specification defines the architecture, protocol, and programming interface for PCIe, which is widely used for connecting peripherals, storage devices, and network interfaces to a computer's motherboard.