module power_of_two_divider ( input clk_in, input reset, output clk_out ); reg [3:0] counter; always @(posedge clk_in or posedge reset) begin if (reset) counter <= 4'b0; else counter <= counter + 1; end // bit 0 is f/2, bit 1 is f/4, bit 2 is f/8, bit 3 is f/16 assign clk_out = counter[3]; endmodule Use code with caution. Even Integer Frequency Dividers
In this example, the frequency_divider module uses a digital logic to perform the frequency division. The output signal divided_clk is generated by comparing the current count with the division ratio.
endmodule
Generate output with 5 input cycles for every 2 output cycles. This is often done with a dual-modulus prescaler (divide by 2 or 3) controlled by a sigma-delta modulator.
module frequency_divider( input clk, // input clock input rst, // reset output divided_clk // divided clock output ); verilog frequency divider
reg [31:0] counter; // counter to keep track of clock cycles
module clk_enable_div8 ( input clk, rst_n, output reg clk_en ); reg [2:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) count <= 0; else count <= (count == 7) ? 0 : count + 1; end assign clk_en = (count == 7); // one cycle wide pulse endmodule This is often done with a dual-modulus prescaler
reg [31:0] counter;
wire [31:0] divided_clk_wire;
Test the divider with a parameterized testbench:
endmodule