Successful OOB handshake results in a stable link at the negotiated speed (1.5, 3, or 6 Gbit/s, depending on capabilities). The host controller's Port Status and Control (PxSCTL) register reflects link-up status via the field (e.g., DET=0x3 indicates a successful link). If OOB fails, the drive will never be visible to software.

With the port engine active, the host must determine what type of device (if any) is attached. AHCI does not assume a SATA drive—it could be an ATAPI device (optical drive), an eSATA hot-plug drive, or a port multiplier.

Understanding these phases illuminates typical failure modes:

To modify the command list base addresses ( CLB ), the port engine must be stopped ( PxCMD.ST = 0) and the command list engine halted ( PxCMD.CR = 0).

The OOB sequence consists of three distinct events:

AHCI drive initialization is a carefully choreographed dance between hardware and software. It begins with analog electrical handshakes (OOB), moves through memory-mapped register configuration, performs device signature detection, and finally establishes a DMA-capable command pipeline. Each phase is atomic—failure at any step prevents the drive from reaching the ready state. For developers and system administrators, knowing these phases turns cryptic boot failures (e.g., "SATA link down" or "DRDY timeout") into diagnosable checkpoints. As NVMe drives supplant SATA for performance-critical roles, AHCI remains the backbone of commodity storage, and its initialization logic will continue to serve billions of legacy and current systems. Understanding it is not merely academic—it is a practical necessity for low-level storage engineering.